VLSI Design

Introduction

Semiconductor manufacturing technology is one of the most impressive technological achievements. Within a single human lifetime we have went from not having transistors, to designing microscopic chips that contain billions of them. In this article we’ll go into how standardizing hardware designs allows for these more complicated designs. For another look a the CMOS technology see my previous article.

Background Knowledge

The first semiconductors had 2 transistors in each chip. In the early 1960’s low-density fabrication processes allowed for around 10 transistors to be manufactured on a chip. Early computers only used 4-10 discrete gates per component and these components were built into circuit boards that handled the connections between them.

Very Large Scale Integration (VLSI) technology emerged to maximize reliability and speed by minimizing connections to external chips and packing all the logic into a single chip. The packing density of VLSI chips also made it attractive for computer memory as more memory would take up less space. Modern VLSI technology allows for chips with billions of transistors to be manufactured. VLSI technology helps to reduce the size of circuits, the effective cost of the devices, and also allows for faster operating speed for the devices. Cheap microcontrollers and other semiconductor devices made at scale use very small die sizes to increase the yield per silicon wafer and reduce the cost per component.

CMOS circuit dissipate very little power when switched. This makes them very attractive for designing logic chips due to the lower power requirements. The CMOS transistors are a type of field effect transistor (FET) that has a gate that controls the current passing through the transistor when a voltage is applied to the gate. The gate needs to reach a threshold voltage to be able to start conducting current through the transistor. To make the channel conductive, the \(V_{gs}\) needs to be greater than the threshold voltage, and the source voltage must be greater than the drain voltage. Below is a simple image of a transistor.

For these transistors the width of the polysilicon gate layer \(L\) defines the maximum current. CMOS technology combines NMOS and PMOS transistors each that have a n-diffusion well or a p-diffusion well respectively. Typical CMOS processes use a 300mm p-type silicon wafer as the substrate that the chip is built on. A series of masking steps on this silicon base creates the layers in the circuit on which materials like Tungsten, or other metals can be vapor deposited during the wafer fabrication process.

Examples

Now we can look at some early chip designs and see exactly how rising complexity of circuits necessitated automated design tooling and how standardizing components of chip designs help for making more complicated circuits.

Intel 4004

Here is a diagram of the Intel 4004. It was one of the first commercial digital microprocessors. The Intel 4004 was the commercial MOS-LSI chip developed in 1971 as an early calculator chip for the commercial calculator market. It was in essence a 4-bit computer that powered a 4-function business calculator. or manufacturing, It used a 10 um process. It included 2300 transistors, and operated at a speed of 400-800 kH. By looking at the design below we can see the individual transistors and see how the data lines flow around the processor.

This is the Intel 4003. It is simple enough that we can see all of the individual transistors in this diagram along with the input, output, and ground pads.

Finally here is a modern Amtel 2560 chip and we can see just how much the complexity increased. The window inset shows the detail for just one of the memory blocks. There is just no way that something like this can be designed entirely by hand.

Modern EDA tools use a high-level hardware language that specifies the operation of a logic chip, and this behavior is then translated into physical chip design. One way to automate this is to individually design simple components wit gates and capacitors in such a way that a computer can arrange them in the proper ordering for the desired logical behavior. Enter the Standard Cell…

Standard Cell

During the improvement of fabrication processes it was discovered that simply migrating an existing chip design to a smaller process node may not always result in a viable chip. To allow for existing high-level designs to be made on smaller process nodes, standardized cells were developed. The standard cell is designed around power, area, and performance and are used in digital cell libraries. These standard cells are pre-defined, and pre-characterized digital designs. The standard cell sizes are based on the height of the cells determined by number of tracks, beta-ratio, pitch, and transistor widths. Both the VDD and the VSS layers are built in the first metal layer of the cell. The N-well region is near the VDD rail and the P-well region is near the VCC rail. This means that the PMOS transistors are made in the N-well and the NMOS transistors are made in the P-Well. Standard cell types are classified by the density and the threshold voltage

The height of the standard cell is the number of tracks in it. The standard cell tracks are a line onto which the metal or polysilicon can be drawn. One track is M1 pitch. The equation for the height of the standard cell is
$$\text{pitch}\times(N-1)$$
Where N is the number of tracks. Small cell heights are used for high-density designs because smaller cells have low power consumption. Taller standard cells have better performance , but requires more power. The opposite occurs with the smaller standard cells. They have reduced performance at the advantage of smaller size and power. Medium cell heights have a good balance between the small and large cell sizes.

Small standard cells are used in mobile applications, embedded controllers and other low-power applications. Medium standard cells are used for general computing, GPU, and general-purpose circuits. Large standard cells cover a wide area, They are used for high speed and high performance computing.

Below we have some example sizes of standard cell heights of 6, 9, 12, and 13T.

There are many different types of standard cells besides the standard logic gates. These other cells are needed to ensure the continuity of power rails, diffusion wells, and other elements. There can also be different lengths of standard cells in addition to the heights. The different lengths allow for proper placement of the critical gate cells by filling the spaces between them with buffer cells, filler cells, delay cells, or decoupling capacitors.

Voltages

Standard cells with low threshold voltage transistors are fast because of the low gate delay. The downside is that they have a large leakage. High threshold voltage transistors have low leakage and a high gate delay. The sub-threshold leakage varies exponentially with the threshold voltage but the dependency of delay with respect to threshold voltage is weaker. High threshold voltage cells are used to reduce leakage in non-critical paths while the standard and low threshold voltage are used for critical path timings.

Chip

Below I have an example of a simple chip design that I generated using the Skywater OpenLane workflow. The pink lines are all outlines of each of the standard cell elements. We will look further into some of these standard cell types and why we need them in a final chip design.

Clock Buffer

A clock buffer is used to maintain the integrity of the clock signals throughout the chip. Here are some examples of clock buffers of lengths 6, 12, and 16.

  • Length 4 Clock Buffer
  • Length 12 Clock Buffer
  • Length 16 Clock Buffer

Power Rails

The power rails Bring the power and ground connections to the individual cells. In this image we can see the how the power plane is connected to the standard cells. The standard cells are separated by the solid magenta line. The two wide vertical metal traces are power and ground wires.

As we can see above the horizontal power and ground rails are alternated. This means that the cells are “mirrored” so that vertically adjacent cells share the same power and ground rails.

On the right, we can zoom in on the connection points between the vertical power rails and the horizontal power rails for the standard cells.

Filler Cell

The Filler cells provide continuity to the power and ground rails in a VLSI design. It also provides n-well continuity. These cells are made from an n-well and a p-substrate and are non-functional from a logical perspective. Below are some filler cells from the Skywater 130 library.

Decap Cell

Decap Cells are decoupling capacitors that are introduced in a VLSI standard cell library. They maintain a voltage across the power rails in the event of a voltage drop to avoid power glitches. These capacitors are placed between the power and the ground lines. Below we have some images of decap cells

  • Decap 3 Cell
  • Decap 8 Cell
  • Decap 12 Cell

Endcap cells are used to terminate a row of standard cells. You can think of them as a special case of decap cells. In this example we can also see how the cells are a mirror image of eachother around the power rail. on the left side of the chip.

Delay Gate

Delay gates ensure that the output of a logic gate has stabilized before being propagated into the circuit. These are critical for proper behavior of the chip and are used in validating timing closures(the bane of many chip designers). Here we have some example of different delay gates from the Skywater 130 library.

Inverter

Finally we can get to the logic gates, the simplest of which is the inverter. It is easy to see how the inverter is designed from the transistors formed between the diffusion wells. For more on the inverter see my previous article.

AND Gate

Below is an AND gate implementation, previously explained here: previous article.

NAND Gate

NAND gates are important because you can use combinations of NAND gates to create any logic function. They are considered a universal gate. Below are some skywater NAND cells.

XOR Gate

An XOR gate acts like a conditional inverter. Below we have some examples of an XOR gate.

XNOR Gate

Below are some examples of an XNOR gate

D Flip-Flop

The D Flip-Flop is a better alternative than the JK Flip-FLop and SR Flip-Flop. It is popular with digital electronics and used for counters and shift registers. The DFF can only change from the edge of a clock. At all other times the output is unaffected. Below are some skywater implementations of a D Flip-flop

We can see that this gate is much more complicated and thus larger than some of the previous gates in the library.

Future

The semiconductor market is expected to reach more than $1T by 2030 with China being the largest downstream user. Computers, automotive, and communications applications are the largest end users of semiconductors as logic chips represented 60% of semiconductor sales with Microprocessors and MEMS devices with automotive applications are expected to be the top revenue driver.

Modern semiconductor manufacturing is concentrated in Taiwan, South Korea, China, and Japan. Taiwan accounts for most of the fabrication capabilities for the advanced chips, while South Korea has the largest share of memory chip fabrication. This geographical concentration of manufacturing, as exposed by the pandemic, creates a logistics bottleneck. To mitigate the risks for these critical chips the US and other countries are diversifying their supply chains. In the US the CHIPS act has set billions of dollars aside to incentivize domestic development of chip fabrication facilities. These new development projects total almost $500B and are spread across 28 states. The investment of resources shows just how important it is to secure the supply of semiconductor devices.

As domestic semiconductor manufacturing increases in scale, so will the need for workers and knowledge required to create new chip designs. More capable chips require more complicated logic, which is made easier by all of the previously mentioned advancements in VLSI design with more of the details being abstracted away from the designer. Nevertheless it is essential to maintain a knowledge of the basics of VLSI design as we develop and employ more powerful design tools.

Sources

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