Building a NIOS2 Soft Processor

Contents

What is a Soft Processor?

A Soft processor is a computer processor that is implemented in a programmable gate array. This allows the processor to be reconfigured or even replaced with another design without building an entirely different circuit board. Unlike a hard processor that must be fabricated by a semiconductor manufacturing company, soft processors can be distributed as intellectual property like software once they are designed. This allows digital designers to offload the task of creating their own processors and simply use pre-designed processors with multiple versions or peripherals. Below is an example of a chip containing 4 of the newest Avispado RISC-V IP cores From Semidynamics. Imagine the time and effort saved by using these designs instead of designing your own!

Equipment List

For this project, I used a DE-10 Lite development board. This board houses the Altera MAX-10 FPGA along with some other peripherals such as RAM chips, Accelerometers, VGA Ports, and others that we will not be going into in this article. To make designs for the MAX-10 on this board, we need to use the Altera design software Quartus Prime. This software includes pin planning tools, a system designer tool, software build tools, and others for debugging. This is a very complex and capable piece of software, but for this article, we will mostly focus on the Qsys system designer and the Eclipse-based Software build tools. I am currently using the lite software version that can be obtained from the Intel/Altera website.

Creating the NIOS 2 Processor

The scalability and modularity that makes soft processors attractive also gives us a more complicated design process as we have choices as to what we would like to include in our hardware design. The image below was taken from the Nios2 Hardware Development Tutorial document and shows the minimum requirements for a Nios 2 System. The processor core is connected to the other components using an interconnect bus. In addition to the processor, we need the JTAG/UART module to connect for programming the system software. We need a timer, some on-chip RAM, and a unique system ID number. The on-chip ram will be used to store and run our software image. The system ID number is used when we build the software to ensure that the software build is compatible with the version of the system we have designed.

From these components, we can follow the procedure below to build our hardware system.

First, open the Quartus Prime software.

Click on the New-Project Wizard and click next. Select your working directory and project name.

Click Next and select project template as the project type.

Hit next and then select the baseline pinout for the Max10 DE10Lite

Press Next and then on the Summary Screen click ‘Finish’.
For a sanity check, compile your design and upload it to the board.

Uploading a Bitstream

To upload an FPGA bitstream to the DE10-lite board, make sure that the board is plugged in.
In quartus prime under tools, select programmer.

Click ‘Auto-Detect’ and select your device.

Press ‘OK’ and your device should show up in the programmer window.

Double-click the ‘<none>’ text under the ‘File’ table header to select a new file for programming. Under output_files, select your time-limited .sof file compiled previously, then hit open. This design is time limited because we need a license for the NIOS2 IP Core. Without a license, you can still use the design, but it will eventually time out.

Check the program/configure box next to your device and hit the ‘Start’ button on the left-hand side. This will send the hardware design bitstream to the FPGA and configure the device.

When you can see the LEDs on the board light up then you know it has been programmed properly.

Building the NIOS2 Design using Qsys

Open your Quartus 2 project.Under tool select Qsys. You should see something that looks like this image below.

We need to add 6 elements as per the example design diagram at the beginning of the section. From the IP Catalog add the following items to the design with default settings: NIOS 2 Processor, JTAG UART, Interval Timer, PIO, System ID Peripheral, and On-Chip Memory. Ignore any error messages at this stage. In the system contents window connect the NIOS2 processor instruction and data master lines to the onchip_memory_2 S1 port.

Double click on the nio2_gen_0 block to open up the processor configuration window. Once it opens you should see something that looks like this. The Nios2 processor has two different versions, a fast and an economy version. The economy version has slower performance but takes up fewer resources on the FPGA, while the fast version has better performance but it is bigger. We can leave this selection at its default Nios II/f (fast) version.

In this window click on the ‘Caches and Memory Interfaces’ tab. Reduce the size of the instruction cache to 2 kB.

Next Select the ‘Vectors’ Tab and change the reset and exception vectors to the onchip_memory2_0.s1 .

Click Finish to exit the processor core configuration window.

right click on the nios2 block in the system contents window and hit edit.Connect all the clk input ports with the clk output port of the clock.

Connect all reset input ports to the reset line of the clock.

Connect all S1 and Slave ports to the instruction and data master lines.

Connect the UART and Timer to the Irq line going to the NIOS2 processor core.

Double-click the PIO export column. This allows the PIO block to be seen and accessed by hardware components that are outside the Nios2 system.

Right-Click the system ID peripheral and click edit.Change the number for the system ID. then hit finish

Right click on the onchip_memory2_0 and select edit and change the memory size to 65536 bytes. Uncheck the initialize memory content box and hit ‘Finish’

Under the ‘System’ dropdown menu click ‘Assign Base Addresses’. This automatically arranges the memory map addresses. Save the System.

Under ‘Generate’ Click ‘Generate HDL’.

Click ‘Generate’.

Once the generation process has finished, Click finish in the bottom corner of the Qsys window.

When you go back to the quartus project, remember to add these .qip and .sip files to your project.

Adding NIOS2 Desing Files to Quartus Project

In Quartus under the project tab select add/remove files from project.


Click the 3 dots next to the filename and navigate to the directory that generated the .qip and .sip files.


select the .qip file and click ‘Open’
Press ‘Ok’ to add it to your project.

Now that your project has access to the design files of the system that you had previously generated.

Adding NIOS2 Implementation to Top File

In the sections above we have only designed the Nios2 processor system, we still have to place it in our design file. Luckily as part of the generation procedure the Qsys Designer gives us a file that can be used as a template for initializing an instance of our system into the main design file.

Open your Quartus Project.
Open the file that ends in inst.v This is a template file that gives you the code to instantiate your system in the top level file.

Copy this code and insert it into the top file in your project. Add the Max10_Clk1_50 signal as the clock input signal for the NIOS2 system. You should also connect the ARDUINO_RESET_N to the reset port, and the LEDR to the PIO port.

Compile the design by double clicking the ‘Compile Design’ button in the task window.

When the design complies properly you should see green arrows as shown above. You can then program the board as described in the earlier step.

Creating a NIOS2 Software Image

Open your quartus project.
Under ‘tools’ select ‘NIOS 2 Software build tools for Eclipse’.
Make a new workspace folder in the project folder

Select File -> New NIOS 2 application and BSP from Template.

Click on the 3 dots next to the SOPC file name, navigate to the .sopcinfo file, and click Open. The SOPC file was generated based on the hardware design and contains information about the specific hardware design that the software BSP needs to know about.

Select ‘Hello World’ under the project template, and make a name for your software project. Then Click ‘Finish’

In the project explorer, select the Project and open the hello_world.c file. Edit the hello message to a custom placeholder text. This is the boilerplate code for our software image.

Ensure that your board is connected to the computer and is configured with your NIOS2 project from the previous session.

Right Click the project folder in the Project explorer tab and select ‘Debug as NiosII Hardware’. if you do not see any hardware target connections, click the refresh connections button.

Once you verify that your board is connected, click ‘Debug’. If you are prompted to switch to a debug perspective, say yes. Your debug session starts in a paused state therefore you need to press the resume button (f8) to see the output of your program on the console window at the bottom.

If you make any changes to the underlying hardware from Quartus or Qsys you need to update the BSP in the software project. To do this right click on the BSP project, under the NIOS 2 option click ‘Generate BSP’. You can then rebuild the project.

Conclusion

Thanks for sticking through till the end! I know it was a long one. This post gave a quick tutorial about how to design an embedded processor system for an FPGA using Intel/Altera tools. We also looked at building a simple software application that runs on our custom hardware design. In future articles we will explore the design tools for other FPGA manufacturers and get into custom instructions as well as interfacing with external peripheral devices.

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